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1 for more information www.linear.com/lt3086 typical a pplica t ion fea t ures descrip t ion 40v, 2.1a low dropout adjustable linear regulator with monitoring and cable dr op compensation the lt ? 3086 is a multi-feature, low dropout, low noise 2.1a linear regulator that operates over a 1.4 v to 40v input supply range. dropout voltage at 2.1 a is typically 330mv. one resistor sets output voltage from 0.4 v to 32 v. output voltage tolerance is guaranteed to 2% over line, load and temperature. the lt 3086 is stable with ceramic output capacitors, requiring a minimum of 10f. the lt 3086s programmable cable drop compensation cancels output voltage errors caused by resistive connec - tions to the load. a master/ slave configuration allows paral - leling of multiple devices for higher load current and heat spreading without external ballast resistor requirements. output current and temperature monitoring along with a power good flag provide system diagnostic and debug capability. internal fault circuitry includes thermal shutdown and current limit with foldback. thermal limit and current limit are also externally programmable. packages include the thermally enhanced 16- lead (5mm 4 mm) dfn , 16- lead tssop , 7- lead dd-pak and 7-lead to-220. l, lt , lt c , lt m , linear technology and the linear logo are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners. 5v, 2.1a usb supply with cable drop compensation transient response with cable drop compensation (cdc) a pplica t ions n wide input voltage range: 1.4v to 40v n 1 resistor sets output voltage: 0.4v to 32v n output current: 2.1a n 2% tolerance over line, load and temperature n output current monitor: i mon = i out /1000 n temperature monitor with programmable thermal limit n programmable cable drop compensation n parallel multiple devices for higher current n dropout voltage: 330mv n 1 capacitor soft-starts output and decreases noise n low output noise: 40v rms (10hz to 100khz) n precision, programmable external current limit n power good flag with programmable threshold n ceramic output capacitors: 10f minimum n quiescent current in shutdown: <1a n reverse-battery, -current and -output protection n available in 5mm 4mm 16-lead dfn, 16-lead tssop , 7- lead dd-pak and 7-lead to-220. n programmable linear regulator n post regulator for switching supplies n usb power supplies n high reliability power supplies 3086 ta01 in shdn track temp i mon i lim out set cdc pwrgd r pwrgd v pwrgd *see applications information for inductance effects associated with r wire gnd lt3086 v in 6v to 15v to adc 0.8v at 2.24a full-scale v temp 10mv/c 25c = 250mv v out 10f 10f r set 90.9k + 1.1k 1% r cdc 1% r cdc 1% r line1 cable r line2 r mon 357 1% 82.5k 1% 100k v load 5v at 2.1a load r cdc = r mon ? r set 3000 ? r wire r wire = r line1 + r line2 * 0 80 160 560 640 720 800 240 320 400 480 time (s) output voltage (v) load current (a) 3060 ta04b 5.8 5.6 5.2 4.8 4.4 2 5.4 5.0 4.6 4.2 1 0 v in = 6v r mon = 357 r wire = 0.24 r cdc = 46.4k v out with cdc v load without cdc v load with cdc ?i load = 0.5a to 1.5a lt3086 3086fa
2 for more information www.linear.com/lt3086 a bsolu t e maxi m u m r a t ings in pin voltage ......................................................... 45v out pin voltage ...................................................... 3 6 v input - to - output differential voltage ( note 2) .......... 45 v set pin voltage ............................................... C 0.3, 36 v shdn pin voltage ................................................... 45v cdc pin ( internally clamped , current into pin ) ....... <8 ma i mon pin voltage ................................................ C 0.3, 7 v i lim pin voltage .................................................. C 0.3, 2 v track pin voltage .... C 0.3, internally clamped at 1.25 v temp pin voltage ................................................. 0 v, 5v (note 1) 16 15 14 13 12 11 10 9 17 gnd 1 2 3 4 5 6 7 8 gnd pwrgd track temp shdn in in nc gnd i lim i mon cdc r pwrgd set out out top view dhd package 16-lead (5mm 4mm) plastic dfn t jmax = 125c, ja = 25c/w to 33c/w*, jc = 4.3c/w exposed pad ( pin 17) is gnd, must be soldered to pcb fe package 16-lead plastic tssop 1 2 3 4 5 6 7 8 top view 16 15 14 13 12 11 10 9 gnd i mon /i lim cdc r pwrgd set out out gnd gnd pwrgd track temp shdn in in gnd 17 gnd t jmax = 125c, ja = 25c/w to 33c/w*, jc = 10c/w exposed pad ( pin 17) is gnd, must be soldered to pcb r package 7-lead plastic dd front view temp shdn in gnd out set i mon /i lim 7 6 5 4 3 2 1 tab is gnd t jmax = 125c, ja = 15c/w to 19c/w*, jc = 3c/w t7 package 7-lead plastic to-220 temp shdn in gnd out set i mon /i lim front view tab is gnd 7 6 5 4 3 2 1 t jmax = 125c, ja = 34c/w, jc = 3c/w *see applications information section. p in c on f igura t ion pwrgd pin voltage ......................................... C 0.3, 36 v r pwrgd pin voltage ......................................... C 0.3, 36 v output short - circuit duration .......................... in definite operating junction temperature ( notes 3, 5, 12) e- grade , i - grade ................................ C 40 c to 125 c mp - gr ade .......................................... C 55 c to 125 c storage temperature range ...................... C 65 to 150 c lead temperature ( soldering , 10 sec ) ( tssop , dd - pak , to -220 only ) ........................... 30 0 c lt3086 3086fa
3 for more information www.linear.com/lt3086 parameter conditions min typ max units minimum input voltage (note 4) i load = 2.1a, ?v out = C1% l 1.4 1.55 v reference voltage v set (notes 3, 5) v in = 1.55v, i load = 1ma 1.55v < v in < 40v, 1ma < i load < 2.1a l 396 392 400 400 404 408 mv mv reference current i set v in = 1.55v, i load = 1ma 1.55v < v in < 40v, 1ma < i load < 2.1a l 49.5 49 50 50 50.5 51 a a line regulation v set i set v in = 1.55v to 40v, i load = 1ma l l C0.12 0.1 C0.03 0.8 mv a load regulation v set (notes 6, 7) i set i load = 1ma to 2.1a, v in = v out + 0.55v l l 0.25 0.02 1 0.08 mv a minimum load current (note 16) l 1 ma dropout voltage v in = v out(nominal) , (notes 7, 8) i load = 1ma l 10 65 100 mv mv i load = 100ma l 100 135 160 mv mv i load = 500ma l 150 195 235 mv mv i load = 1.5a l 260 335 425 mv mv i load = 2.1a l 330 415 540 mv mv gnd pin current v in = v out(nominal) + 0.55v, (notes 7, 9) i load = 0a i load = 1ma i load = 100ma i load = 500ma i load = 1.5a i load = 2.1a l l l l l l 1.2 1.3 1.8 4.5 23 44 2.4 2.6 3.6 9 46 88 ma ma ma ma ma ma e lec t rical c harac t eris t ics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. lead free finish tape and reel part marking* package description temperature range lt3086edhd#pbf lt3086edhd#trpbf 3086 16-lead (5mm 4mm) plastic dfn C40c to 125c lt3086idhd#pbf lt3086idhd#trpbf 3086 16-lead (5mm 4mm) plastic dfn C40c to 125c lt3086efe#pbf lt3086efe#trpbf 3086fe 16-lead plastic tssop C40c to 125c lt3086ife#pbf lt3086ife#trpbf 3086fe 16-lead plastic tssop C40c to 125c lt3086mpfe#pbf lt3086mpfe#trpbf 3086fe 16-lead plastic tssop C55c to 125c lt3086er#pbf lt3086er#trpbf lt3086r 7-lead plastic dd-pak C40c to 125c lt3086ir#pbf lt3086ir#trpbf lt3086r 7-lead plastic dd-pak C40c to 125c lt3086mpr#pbf lt3086mpr#trpbf lt3086r 7-lead plastic dd-pak C55c to 125c lt3086et7#pbf n/a lt3086t7 7-lead plastic to-220 C40c to 125c lt3086it7#pbf n/a lt3086t7 7-lead plastic to-220 C40c to 125c lt3086 mpt 7#pbf n/a lt3086t7 7-lead plastic to-220 C55c to 125c consult lt c marketing for parts specified with wider operating temperature ranges. *the temperature grade is identified by a label on the shipping container. consult lt c marketing for information on non-standard lead based finish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ o r d er i n f or m a t ion lt3086 3086fa
4 for more information www.linear.com/lt3086 parameter conditions min typ max units quiescent current in shutdown v in = 40v, v shdn = 0v 0.1 1 a output voltage noise c set = 0.01f , c out = 10f, i load = 2.1a v out = 5v, bw = 10hz to 100khz 40 v rms shutdown threshold v out = off to on v out = on to off l l 1.12 0.85 1.22 1.03 1.32 v v shdn pin current (note 10) 1.55v < v in < 40v v shdn = 0v v shdn = 40v l l 15 1 35 a a temp v oltage (note 13) t j = 25c t j = 125c 0.25 1.25 v v temp error (note 13) 0c < t j < 125c, i temp = 0 0c < t j < 125c, i temp = 0a to 80a C0.09 C0.1 0.09 v v i temp thermal limit current threshold 25c < t j < 125c 95 100 105 a i mon output current v in = v out(nominal) + 0.55v (note 15) i load = 20ma, r mon = 1k i load = 500ma, r mon = 330 i load = 1a, r mon = 330 i load = 1.5a, r mon = 330 i load = 2.1a, r mon = 330 l l l l l 5 440 0.95 1.43 2.02 20 500 1.00 1.50 2.10 75 560 1.05 1.57 2.18 a a ma ma ma output current sharing error (note 14) r mon = 330, i out(master) = 2.1a C10 0 10 % track pin pull-up current v track = 750mv l 7 15 25 a r pwrgd reference voltage 1.55v < v in < 40v l 390 400 410 mv r pwrgd reference current 1.55v < v in < 40v l 48.75 50 51.25 a r pwrgd reference voltage hysteresis 1.55v < v in < 40v 2.4 mv r pwrgd reference current hysteresis 1.55v < v in < 40v 300 na pwrgd v ol i pwrgd = 200a (fault condition) l 55 200 mv pwrgd internal time delay v ol to v oh (rising edge) l 8 17 25 s pwrgd pin leakage current v pwgrd = 32v, v rpwgrd = 500mv l 1 a cdc reference voltage 1.55v < v in < 40v, i mon = 0v l 390 400 410 mv cdc/v imon voltage gain 1.55v < v in < 40v, 0 < i cdc < 20a, v imon = 800mv to 0 l 0.320 0.333 0.343 v/v ripple rejection v in = 1.9v ( avg ), v ripple = 0.5v p-p , v out = 1v f ripple = 120hz, i load = 2.1a 65 80 db internal current limit v in = 1.55v v in = v out(nominal) + 0.55v (notes 7, 12), ?v out = C5% l l 2.2 2.2 2.4 2.9 a a i lim threshold voltage 1.55v < v in < 40v l 775 800 825 mv input reverse-leakage current v in = C40v, v out = 0 l 2 ma reverse-output current (note 11) v out = 32v, v in = 0, v shdn = 0 1 10 a e lec t rical c harac t eris t ics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: absolute maximum input-to-output differential voltage is not achievable with all combinations of rated in pin and out pin voltages. with the in pin at 45v, the out pin may not be pulled below 0v. the total in to out differential voltage must not exceed 45v. note 3: the lt3086 is tested and specified under pulse load conditions such that t j ? t a . the lt3086e is 100% production tested at t a = 25c and performance is guaranteed from 0c to 125c. performance at C40c to 125c is assured by design, characterization and correlation with statistical process controls. the lt3086i is guaranteed over the full C40c to 125c operating junction temperature range. the lt3086mp is 100% tested over the C55c to 125c operating junction temperature range. note 4: the lt3086 is tested and specified for these conditions with the set pin connected to the out pin, v out = 0.4v. note 5: maximum junction temperature limits operating conditions. the regulated output voltage specification does not apply for all possible combinations of input voltage and output current. limit the output current range if operating at large input-to-output voltage differentials. limit the input-to-output voltage differential if operating at maximum output current . current limit foldback limits the maximum output current as a function of input-to-output voltage. see current limit vs v in C v out in the typical performance characteristics section. note 6: load regulation is kelvin-sensed at the package. lt3086 3086fa
5 for more information www.linear.com/lt3086 note 7: to satisfy minimum input voltage requirements, the lt3086 is tested and specified for these conditions with a 32k resistor between out and set for a 2v output voltage. note 8: dropout voltage is the minimum input-to-output voltage differential needed to maintain regulation at a specified output current. in dropout, the output voltage equals: (v in C v dropout ). for low output voltages and certain load conditions, minimum input voltage requirements limit dropout voltage. see the minimum input voltage curve in the typical performance characteristics section. note 9: gnd pin current is tested with v in = v out(nominal) + 0.55v and pwrgd pin floating. gnd pin current increases in dropout. see gnd pin current curves in the typical performance characteristics section. note 10: shdn pin current flows into the shdn pin. note 11: reverse-output current is tested with the in pin grounded and the out pin forced to a voltage. the current flows into the out pin and out of the gnd pin. note 12: the ic includes overtemperature protection circuitry that protects the device during momentary overload conditions. junction temperature exceeds 125c when the overtemperature circuitry is active unless thermal limit is externally set below 125c by loading the temp pin. continuous operation above the specified maximum junction temperature may impair device reliability. note 13: the temp output voltage represents the average die temperature next to the power transistor while the center of the transistor can be significantly hotter during high power conditions. due to power dissipation and temperature gradients across the die, the temp output voltage measurement does not guarantee that absolute maximum junction temperature is not exceeded. note 14: output current sharing error is the difference in output currents of a slave relative to its master when two lt3086 regulators are paralleled. the device is tested as a slave with v track = 0.693v, r mon = 330 and v set = 0.4v, conditions when an ideal master is outputting 2.1a. the specification limits account for the slave output tracking error from 2.1a and the worst-case error that can be contributed by a master: the maximum deviation of v set from 0.4v and i mon from 2.1ma. note 15: the lt3086 is tested and specified for these conditions with the i mon and i lim pins tied together. note 16: the lt3086 requires a minimum load current to ensure proper regulation and stability. typical dropout voltage guaranteed dropout voltage dropout voltage typical p er f or m ance c harac t eris t ics e lec t rical c harac t eris t ics t a = 25c, unless otherwise noted. output current (a) 0 dropout voltage (mv) 550 500 400 300 200 100 450 350 250 150 50 0 1.2 0.6 3086 g01 2.1 0.9 0.3 1.5 1.8 t j = 125c t j = 25c output current (a) 0 guaranteed dropout voltage (mv) 550 500 400 300 200 100 450 350 250 150 50 0 1.2 0.6 3086 g02 2.1 0.9 0.3 1.5 1.8 t j 125c t j 25c = test points temperature (c) ?75 dropout voltage (mv) 550 500 400 300 200 100 450 350 250 150 50 0 100 ?25 3086 g03 175 0?50 125 150 7525 50 i l = 2.1a i l = 1.5a i l = 1a i l = 500ma i l = 100ma i l = 1ma lt3086 3086fa
6 for more information www.linear.com/lt3086 typical p er f or m ance c harac t eris t ics gnd pin current, v out = 0.4v (heavy load) gnd pin current, v out = 5v (light load) gnd pin current, v out = 5v (heavy load) quiescent current, v out = 0.4v quiescent current, v out = 5v gnd pin current, v out = 0.4v (light load) t a = 25c, unless otherwise noted. input voltage (v) 0 quiescent current (ma) 2.0 1.8 1.4 1.0 0.2 1.6 1.2 0.8 0.6 0.4 0 25 3086 g07 40 5 30 35 20 10 15 t j = 25c r set = 0 i l = 0 v shdn = v in v shdn = 0 input voltage (v) gnd pin current (ma) 90 70 50 10 80 60 40 30 20 0 3086 g10 t j = 25c v shdn = v in r set = 0 0 7 2 10 31 8 9 64 5 r l = 0.4, i l = 1a r l = 0.267, i l = 1.5a r l = 0.19, i l = 2.1a input voltage (v) gnd pin current (ma) 10 9 7 5 1 8 6 4 3 2 0 3086 g11 t j = 25c v shdn = v in r set = 92k 0 7 2 10 31 8 9 64 5 r l = 10 i l = 500ma r l = 50 i l = 100ma r l = 5k, i l = 1ma input voltage (v) gnd pin current (ma) 3086 g12 t j = 25c v shdn = v in r set = 92k 0 7 2 10 31 8 9 64 5 r l = 2.381 i l = 2.1a r l = 3.333 i l = 1.5a r l = 5, i l = 1a 90 70 50 10 80 60 40 30 20 0 input voltage (v) quiescent current (ma) 2.0 1.8 1.4 1.0 0.2 1.6 1.2 0.8 0.6 0.4 0 3086 g08 t j = 25c r set = 92k i l = 0 v shdn = v in v shdn = 0 0 7 2 10 31 8 9 64 5 input voltage (v) gnd pin current (ma) 10 9 7 5 1 8 6 4 3 2 0 3086 g09 t j = 25c v shdn = v in r set = 0 0 7 2 10 31 8 9 64 5 r l = 0.8 i l = 500ma r l = 4 i l = 100ma r l = 400, i l = 1ma set pin reference voltage set pin reference current quiescent current temperature (c) ?75 set pin reference voltage (mv) 408 406 402 398 394 404 400 396 392 100 ?25 3086 g04 175 0?50 125 150 7525 50 i l = 1ma temperature (c) ?75 set pin reference current (a) 51.0 50.8 50.4 50.0 49.2 50.6 50.2 49.8 49.6 49.4 49.0 100 ?25 3086 g05 175 0?50 125 150 7525 50 i l = 1ma temperature (c) ?75 quiescent current (ma) 2.0 1.8 1.4 1.0 0.2 1.6 1.2 0.8 0.6 0.4 0 100 ?25 3086 g06 175 0?50 125 150 7525 50 v in = 6v v out = 5v i l = 0 v shdn = v in v shdn = 0 lt3086 3086fa
7 for more information www.linear.com/lt3086 typical p er f or m ance c harac t eris t ics r pwrgd pin input current shdn pin input current out over in shutdown threshold r pwrgd pin threshold gnd pin current vs i load gnd pin current vs temperature shdn pin threshold shdn pin input current t a = 25c, unless otherwise noted. output current (a) 0 gnd pin current (ma) 70 60 40 20 50 30 10 0 1.2 0.6 3086 g13 2.1 0.9 0.3 1.5 1.8 v in = v out(nominal) + 0.55v 125c ?40c 25c temperature (c) ?75 shdn pin threshold (v) 1.40 1.35 1.25 1.15 0.95 1.30 1.20 1.10 1.05 1.00 0.90 100 ?25 3086 g14 175 0?50 125 150 7525 50 shdn tied to v in v shdn v in ? 0.3v, v in > v in(min) off to on on to off shdn pin voltage (v) shdn pin input current (a) 20 18 14 10 2 16 12 8 6 4 0 3086 g15 v in = v shdn 0 25 40 5 30 35 20 10 15 r pwrgd pin input current (a) 51.0 50.8 50.4 50.0 49.2 50.6 50.2 49.8 49.6 49.4 49.0 temperature (c) ?75 100 ?25 3086 g19 175 0?50 125 150 7525 50 i l = 0 output rising output falling temperature (c) ?75 shdn pin input current (a) 20 18 14 10 2 16 12 8 6 4 0 100 ?25 3086 g16 175 0?50 125 150 7525 50 v shdn = 40v v shdn = 6v temperature (c) ?75 out over in shutdown threshold (mv) 300 275 225 175 150 100 50 250 200 125 75 25 0 100 ?25 3086 g17 175 0?50 125 150 7525 50 on to off off to on temperature (c) ?75 r pwrgd pin threshold (mv) 408 406 402 398 394 404 400 396 392 100 ?25 3086 g18 175 0?50 125 150 7525 50 i l = 0 output rising output falling gnd pin current (ma) 70 60 40 20 50 30 10 0 3086 g13a temperature (c) ?75 100 ?25 175 0?50 125 150 7525 50 v in = v out(nominal) + 0.55v i l = 2.1a i l = 1.5a i l = 1a i l = 500ma lt3086 3086fa
8 for more information www.linear.com/lt3086 typical p er f or m ance c harac t eris t ics track pin pull-up current i lim pin input current track amplifier input offset track amplifier gain t a = 25c, unless otherwise noted. i lim pin voltage (mv) i lim pin current (a) 10 8 4 0 ?8 6 2 ?2 ?6 ?4 ?10 3086 g25 0 500 800 100 600 700 400 200 300 track pin voltage (v) 0 track pin pull-up current (a) 30 25 15 5 20 10 0 0.8 0.4 3086 g28 1.4 0.6 0.2 1.0 1.2 track amplifier input offset (mv) 10 8 4 0 ?8 6 2 ?2 ?6 ?4 ?10 3086 g26 temperature (c) ?75 100 ?25 175 0?50 125 150 7525 50 track = 750mv track = 0mv track = 400mv track amplifier gain (v/v) 3086 g27 temperature (c) ?75 100 ?25 175 0?50 125 150 7525 50 track = 750mv track = 0mv track = 400mv 0.25 0.24 0.22 0.20 0.16 0.23 0.21 0.19 0.18 0.17 0.15 pwrgd output low voltage pwrgd internal time delay i out /i mon ratio current monitor at light load i lim pin threshold voltage output current (a) 0 i out /i mon ratio (a/a) 1060 1050 1030 1010 1000 980 960 1040 1020 990 970 950 940 1.2 3086 g22 2.1 1.5 1.8 0.9 0.3 0.6 i mon = v imon /r mon i mon tied to i lim r mon = 330 v in = v out + 0.55v t j = 25c t j = ?40c t j = 125c temperature (c) ?75 current monitor (v imon /r mon ) (a) 40 35 25 15 5 30 20 10 0 100 ?25 3086 g23 175 0?50 125 150 7525 50 i l = 20ma i l = 0 i mon tied to i lim r mon = 1k v in = v out + 0.55v temperature (c) ?75 i lim pin threshold (mv) 825 820 810 805 795 785 815 800 790 780 775 100 ?25 3086 g24 175 0?50 125 150 7525 50 temperature (c) ?75 pwrgd output low voltage (mv) 200 180 140 100 20 160 120 80 60 40 0 100 ?25 3086 g20 175 0?50 125 150 7525 50 i pwrgd = 200a temperature (c) ?75 pwrgd internal time delay (s) 22 21 19 17 16 14 12 20 18 15 13 11 10 100 ?25 3086 g21 175 0?50 125 150 7525 50 i pwrgd = 200a v ol to v oh lt3086 3086fa
9 for more information www.linear.com/lt3086 typical p er f or m ance c harac t eris t ics internal current limit vs temperature temp pin error i temp thermal limit threshold internal current limit vs v in C v out track pin pull-up current cdc pin reference voltage cdc amplifier gain cdc amplifier gain cdc pin internal clamp fault current t a = 25c, unless otherwise noted. temperature (c) ?75 cdc/v imon voltage gain (v/v) 0.343 0.341 0.337 0.333 0.327 0.325 0.339 0.335 0.331 0.329 0.323 100 ?25 3086 g31 175 0?50 125 150 7525 50 v imon = 800mv to 0mv r cdc = r cdc (k) 0 cdc/v imon voltage gain (v/v) 0.343 0.341 0.337 0.333 0.327 0.325 0.339 0.335 0.331 0.329 0.323 70 20 3086 g32 100 3010 80 90 6040 50 v imon = 800mv to 0mv t j = 125c t j = 25c t j = ?40c cdc pin voltage (v) 0 cdc pin current (ma) 8 7 5 3 6 4 2 1 0 7 2 3086 g33 10 31 8 9 64 5 t j = 125c t j = 25c t j = ?40c v out > v out(nominal) track pin pull-up current (a) 30 25 15 5 20 10 0 temperature (c) ?75 100 ?25 3086 g29 175 0?50 125 150 7525 50 track = 750mv track = 0 temperature (c) ?75 cdc pin reference voltage (mv) 408 406 402 400 396 404 398 394 392 100 ?25 3086 g30 175 0?50 125 150 7525 50 r cdc = r mon = 0 i l = 0 temperature (c) ?75 current limit (a) 3.0 2.7 2.1 1.5 0.6 0.3 2.4 1.8 1.2 0.9 0 100 ?25 3086 g37 175 0?50 125 150 7525 50 v in = 1.55v v out = 0v temperature (c) temp pin error (c) 2.5 2.0 1.0 0 ?2.0 1.5 0.5 ?0.5 ?1.5 ?1.0 ?2.5 3086 g34 25 75 150 100 125 50 temp = v temp /(10mv/c) i temp = 80a i temp = 0 temperature (c) thermal limit threshold (a) 105 104 102 100 96 103 101 99 97 98 95 3086 g35 25 75 150 100 125 50 temp = v temp /(10mv/c) rising falling input/output differential (v) current limit (a) 3.0 2.7 2.1 1.5 0.3 2.4 1.8 1.2 0.6 0.9 0 3086 g36 0 25 40 5 30 35 20 10 15 t j = 125c ?v out = ?5% t j = ?40c t j = 25c lt3086 3086fa
10 for more information www.linear.com/lt3086 frequency (hz) ripple rejection (db) 100 90 70 50 10 80 60 40 30 20 0 3086 g42 10 100 100k 1m 10m 10k1k c set = 0 c set = 10nf c out = 22f v temp = 0.25v v in = 5.7v + 50mv rms ripple c out = 10f frequency (hz) ripple rejection (db) 100 90 70 50 10 80 60 40 30 20 0 3086 g41 i l = 2.1a, c set = 0, v temp = 0.25v, v in = 1.6v + 50mv rms ripple (for v out = 0.4v) v in = 5.7v + 50mv rms ripple (for v out = 5v) 10 100 100k 1m 10m 10k1k v out = 5v v out = 0.4v c out = 10f c out = 22f typical p er f or m ance c harac t eris t ics ripple rejection vs temperature 5v, 2.1a ripple rejection vs v in C v out 5v, 1a ripple rejection vs v in C v out t a = 25c, unless otherwise noted. ?75 100 ?25 175 0?50 125 150 7525 50 ripple rejection (db) 100 90 70 50 10 80 60 40 30 20 0 3086 g43 i l = 2.1a, c set = 0, v temp = 0.25v, v in = 1.9v + 0.5v p-p ripple (for v out = 0.4v, 1v) v in = 5.9v + 0.5v p-p ripple (for v out = 5v) ripple at f = 120hz v out = 1v v out = 5v v out = 0.4v temperature (c) 0.2 0.3 1.0 0.5 1.2 0.6 0.4 1.1 0.9 0.7 0.8 ripple rejection (db) 100 90 70 50 10 80 60 40 30 20 0 3086 g44 ripple at f = 1mhz 50mv rms ripple on v in i l = 2.1a c out = 10f c set = 10nf v temp = 0.25v ripple at f = 100khz ripple at f = 10khz average input-to-output differential (v) 5v, 2.1a input ripple rejection 5v, 1a input ripple rejection reverse-output current reverse-output current overshoot pull-down current input ripple rejection output voltage (v) 3086 g40 0 20 3632 4 24 28 168 12 output overshoot pull-down (ma) 30 25 15 5 20 10 0 v in > v out v set = 500mv current flows through out pin to gnd output voltage (v) 3086 g38 0 20 32 4 24 28 16 8 12 reverse output current (ma) 0.6 0.5 0.3 0.1 0.4 0.2 0 t j = 25c v in = 0v v out = v set = v rpwrgd current flows through pins to ground out, r pwrgd set temperature (c) ?75 reverse output current (a) 70 60 40 20 50 30 10 0 100 ?25 3086 g39 175 0?50 125 150 7525 50 v in = 0v v shdn = 0v v out = 5v r set = 92k r pwrgd = 82k r pwrgd set out frequency (hz) ripple rejection (db) 100 90 70 50 10 80 60 40 30 20 0 3086 g42a 10 100 100k 1m 10m 10k1k c set = 0 c set = 10nf v temp = 0.25v v in = 5.5v + 50mv rms ripple c out = 10f c out = 22f 0.2 0.3 1.0 0.5 1.2 0.6 0.4 1.1 0.9 0.7 0.8 ripple rejection (db) 100 90 70 50 10 80 60 40 30 20 0 3086 g44a ripple at f = 100khz 50mv rms ripple on v in c out = 10f c set = 10nf v temp = 0.25v ripple at f = 1mhz ripple at f = 10khz average input/output differential (v) lt3086 3086fa
11 for more information www.linear.com/lt3086 reference current load regulation reference current line regulation reference voltage line regulation minimum input voltage output noise spectral density, c set = 0 output noise spectral density vs c set rms output noise vs load current, c set = 0 rms output noise vs load current, c set = 10nf reference voltage load regulation change in set pin reference voltage (mv) 1.0 0.8 0.4 0 ?0.8 0.6 0.2 ?0.2 ?0.6 ?0.4 ?1.0 3086 g45 temperature (c) ?75 100 ?25 175 0?50 125 150 7525 50 v in = v out(nominal) + 0.55v i l = 1ma to 2.1a i l = 1ma to 1.5a change in set pin reference current (na) 80 70 50 30 60 40 20 10 0 3086 g46 temperature (c) ?75 100 ?25 175 0?50 125 150 7525 50 v in = v out(nominal) + 0.55v i l = 1ma to 2.1a i l = 1ma to 1.5a frequency (hz) output noise spectral density (v/ hz) 3086 g49 10 100 100k 10k 1k c set = 100pf c set = 100nf c set = 10nf c set = 1nf 10 1 0.1 0.01 v out = 5v i l = 2.1a c out = 10f v temp = 0.25v load current (a) output noise voltage (v rms ) 350 300 200 100 250 150 50 0 3086 g50 v out = 5v v out = 1.2v v out = 3.3v v out = 2.5v v out = 0.4v 100 1m 1 10 100m 10m c out = 10f c out = 22f f = 10hz to 100khz v temp = 0.25v load current (a) output noise voltage (v rms ) 70 60 40 20 50 30 10 0 3086 g51 v out = 5v v out = 0.4v 100 1m 1 10 100m 10m c out = 10f c out = 22f f = 10hz to 100khz v temp = 0.25v minimum input voltage (v) 1.8 1.6 1.2 0.8 0.2 1.4 1.0 0.6 0.4 0 3086 g47 temperature (c) ?75 100 ?25 175 0?50 125 150 7525 50 i l = 2.1a i l = 100ma frequency (hz) output noise spectral density (v/ hz) 3086 g48 10 100 100k 10k 1k v out = 5v v out = 1.2v v out = 3.3v v out = 2.5v 10 1 0.1 0.01 i l = 2.1a c out = 10f v temp = 0.25v v out = 0.4v typical p er f or m ance c harac t eris t ics temperature (c) ?75 change in set pin reference voltage (mv) 1.0 0.9 0.7 0.5 0.1 0.8 0.6 0.4 0.3 0.2 0 100 ?25 3086 g046a 175 0?50 125 150 7525 50 v in = 1.55v to 40v i l = 1ma temperature (c) ?75 change in set pin reference current (na) 0 ?10 ?30 ?50 ?20 ?40 ?60 ?70 ?80 100 ?25 3086 g046b 175 0?50 125 150 7525 50 v in = 1.55v to 40v i l = 1ma dd-pak/ to-220 dfn/tssop lt3086 3086fa
12 for more information www.linear.com/lt3086 typical p er f or m ance c harac t eris t ics output voltage noise load transient response load transient response rms output noise vs load current rms output noise vs feedforward capacitor (c set ) t a = 25c, unless otherwise noted. load current (a) output noise voltage (v rms ) 60 40 20 50 30 10 0 3086 g52 100 1m 1 10 100m 10m f = 10hz to 100khz v out = 0.4v v temp = 0.25v c out = 100f c out = 10f c out = 22f c out = 47f feedforward capacitor c set (f) 10p 100p 100n 10n 1n output noise voltage (v rms ) 250 225 175 125 25 200 150 100 75 50 0 3086 g53 f = 10hz to 100khz i l = 2.1a c out = 10f v temp = 0.25v v out = 5v v out = 1.2v v out = 2.5v v out = 0.4v v out = 3.3v v out = 5v r set = 92k c set = 10nf c out = 10f i l = 2.1a f = 10hz to 100khz 3086 g54 v out 100v/div time 1ms/div time (s) 0 output voltage deviation (mv) load current (a) 200 50 ?50 150 ?150 2 100 0 ?100 3 1 0 100 3086 g55 160 20 120 140 80 40 60 v in = 5.5v v out = 5v c out = 10f c set = 0 c set = 10nf ?i l = 500ma to 1.5a time (s) 0 output voltage deviation (mv) load current (a) 300 200 ?200 2 100 0 ?100 3 1 0 200 3086 g56 320 40 240 280 160 80 120 v in = 5.5v v out = 5v c set = 10nf ?i l = 210ma to 2.1a c out = 10f ceramic + 100f tantalum c out = 10f ceramic time (ms) 0 output voltage deviation (mv) input voltage (v) 15 0 ?10 10 12 8 5 ?5 10 6 4 0.5 0.6 0.7 3086 g57 1.0 0.1 0.8 0.9 0.4 0.2 0.3 i l = 2.1a v out = 5v c out = 10f ?v in = 5.55v to 12v time (s) 0 output voltage (v) shdn pin voltage (v) 6 3 1 5 0 1.0 4 2 1.5 0.5 0 60 80 90 3086 g58 140 100 120 4020 c out = 10f r set = 92k c set = 0 r l = 2.38 (i l = 2.1a) r l = 5k (i l = 1ma) feedforward capacitor, c set (f) start-up time (ms) 3086 g59 10p 100p 100n 10n 1n v out = 5v v out = 1.2v v out = 3.3v v out = 2.5v 100 10 1 0.1 0.01 i l = 1ma settling to 1% start-up response start-up time vs c set line transient response lt3086 3086fa
13 for more information www.linear.com/lt3086 p in func t ions (dfn/tssop/dd-pak/to-220) gnd (pins 1, 16, exposed pad pin 17/pins 1, 8, 9, 16, exposed pad pin 17/pin 4/pin 4): ground. the exposed pad of the dfn and tssop packages as well as the tab of the dd-pak and to-220 packages is an electrical con- nection to gnd. to ensure proper electrical and thermal performance, tie the exposed pad or tab directly to the remaining gnd pins of the relevant package and the pcb ground. gnd pin current is typically 1.2 ma at zero load and increases to about 44ma at full load. i lim (pin 2/pin 2/pin 1/pin 1): external current limit programming. this pin externally programs current limit if connected to i mon and a resistor to gnd. current limit activates if the voltage at i lim equals 0.8 v. current limit equals : 1000 ? (0.8v/r mon ). an internal clamp typically limits the i lim voltage to 1v . if external current limit is set to less than 1 a, connect a series 1 k-10nf network in parallel with the r mon resistor for stability. internal current limit foldback overrides externally programmed current limit if v in C v out differential voltage is excessive. if external cur- rent limit programming is not used, then ground this pin. i mon (pin 3/pin 2/pin 1/pin 1): output current monitor. this pin sources a current equal to 1/1000 of output load current. connecting a resistor from i mon to gnd programs a load current dependent voltage for monitoring by an adc. if i mon connects to i lim , current limit is externally programmable. cdc (pin 4/pin 3/na/na): cable drop compensation. connecting a single resistor (r cdc ) between the cdc and set pins provides programmable cable drop compensa- tion that cancels output voltage errors caused by resistive connections to the load. a resistor (r mon ) from i mon to gnd is also required to enable cable drop compensation. choose r mon first based on required current limit. r mon = 0.8v ? 1000/i lim calculate the value of r cdc with this formula: r cdc = (r mon ? r set )/(3000 ? r wire ) where r wire is the total cable or wire resistance to and from the load. from a practical application standpoint, lt c recommends limiting cable drop compensation to 20% of v out for applications needing good regulation. the limiting factor is variations in wire temperature as copper wire resistance changes about 19% for a 50c temperature change. if output regulation requirements are loose ( e.g., when using a secondary regulator), cable drop compensation of up to 50% may be used. r pwrgd ( pin 5/pin 4/na/ na): power good threshold voltage programming. this pin is the input to the power good comparator. connecting a resistor between out and r pwrgd programs an adjustable power good threshold voltage. the threshold voltage is 0.4 v on the r pwrgd pin, and a 50 a current source is connected from r pwrgd to gnd. if the voltage at r pwrgd is less than 0.4v , the pwrgd flag asserts and pulls low. if the voltage at r p- wrgd is greater than 0.4v , the pwrgd flag de- asserts and becomes high impedance. for most applications, pwrgd is pulled high with a pull- up resistor. calculate the value of r pwrgd with this formula: r pwrgd = (x ? v out(nominal) C 0.4v)/50a where x is normally in the 85% to 95% range. a 17 s deglitching filter suppresses false tripping of the pwrgd flag at the rising edge of pwrgd with instant reset. hysteresis at the r pwrgd pin is typically 0.6% on the 0.4v threshold and the 50a current source. set (pin 6/pin 5/pin 2/pin 2): output voltage program - ming. this pin is the error amplifiers inverting terminal. it regulates to 0.4 v and a 50 a current source is connected from set to gnd. connecting a single resistor from out to set programs output voltage. calculate the value of the required resistor from the formula: r set = (v out C 0.4v)/50a connecting a capacitor in parallel with r set provides output voltage soft-start capability, improves transient response and decreases output voltage noise. the lt3086 error amplifier design is configured so that the regulator always operates in unity-gain. out (pins 7, 8/pins 6, 7/pin 3/pin 3): output. these pin(s) supply power to the load. connect all out pins together on the dhd and fe packages for proper operation. stability requirements demand a minimum 10 f ceramic output capacitor with an esr less than 100 m to prevent oscillations. large load transients require larger output capacitance to limit peak voltage transients. permissible lt3086 3086fa
14 for more information www.linear.com/lt3086 p in func t ions (dfn/tssop/dd-pak/to-220) output voltage range is 0.4 v to 32v. the lt 3086 requires a 1ma minimum load current to ensure proper regula- tion and stability. in ( pins 10, 11/pins 10, 11/pin 5/pin 5): input. these pin(s) supply power to the device. connect all in pins together on the dhd and fe packages for proper opera - tion. the lt3086 requires a local in bypass capacitor if it is located more than a few inches from the main input filter capacitor. in general, battery output impedance rises with frequency, so adding a bypass capacitor in battery powered circuits is advisable. a 10 f minimum input capacitor generally suffices. the in pin(s) withstand a reverse voltage of 45 v. the device limits current flow and no negative voltage appears at out. the device protects itself and the load against batteries that are plugged in backwards. shdn (pin 12/pin 12/pin 6/pin 6): shutdown/uvlo. pulling the shdn pin typically below 1 v puts the lt3086 into a low power state and turns the output off. quiescent current in shutdown is typically less than 1 a. the shdn pin turn- on threshold is typically 1.22v . this pin may either be used as a shutdown function or as an undervoltage lockout function. if using this pin as an undervoltage lockout function, use a resistor divider between in and gnd with the tap point tied to shdn . if using the pin as a shutdown function, drive the pin with either logic or an open-collector/drain with a pull-up resistor. the resistor supplies the pull-up current to the open-collector/drain logic, normally several microamperes, and the shdn pin current, typically less than 10 a at 6 v. if unused, connect the shdn pin to in. temp (pin 13/pin 13/pin 7/pin 7): die junction tem - perature. this pin outputs a voltage indicating the lt3086 average die junction temperature. at 25c , this pin typically outputs 250 mv. the temp pin slope equals 10 mv/c so that at 125 c, this pin typically outputs 1.25 v. this pin does not read temperatures less than 0 c. the temp pin is not meant to be an accurate temperature sensor, but is useful for debug, monitoring and calculating thermal resistance of the package mounted to the pcb. the temp pin also incorporates the ability to program a thermal limit temperature lower than the internal typical thermal shutdown temperature of 165 c. tying a resistor from temp to gnd programs the thermal limit temperature with a 100 a trip point. calculate the value of the resistor from the formula: r temp = t shdn ? 10mv c ? ? ? ? ? ? 100a where t shdn is the desired die thermal limit temperature. there are several degrees of hysteresis in the thermal shutdown that cycles the regulator output on and off. limit the capacitance on the temp pin to less than 100pf. to prevent saturation in the temp output device, ensure that v in is higher than v temp by 250mv. track (pin 14/pin 14/na/na): track pin for paralleling. the track pin allows multiple lt3086s to be paralleled in a master/slave(s) configuration for higher output cur - rent applications . this also allows heat to be spread out on the pcb. this circuit technique does not require ballast resistors and does not degrade load regulation. tying the track pin of the slave device(s) to the i mon /i lim pins of the master device enables this function. if the track function is unused, track is in a default clamped high state. a track pin voltage below 1.2 v on slave device (s) shuts off the internal 50 a reference current at set such that only the 50 a reference current of the master device is active. all set pins must be tied together in a master/ slave configuration. pwrgd (pin 15/pin 15/na/na): power good flag . the p wrgd pin is an open-collector logic pin connected to the output of the power good comparator. pwrgd asserts low if the r pwrgd pin is less than 400 mv. the maximum low output level of 200 mv over temperature is defined for 200a of sink current. if r pwrgd is greater than 400mv, the pwrgd pin de-asserts and becomes high impedance. the pwrgd pin may be pulled to 36 v without damaging any internal circuitry regardless of the input voltage. lt3086 3086fa
15 for more information www.linear.com/lt3086 b lock diagra m 0.05 q power 50 120mv 40k 3086 bd in gnd 100k 100k 900mv 900mv i mon i lim out cdc en en 300mv ? + 120k cable drop comp ? + current monitor + ? internal ilimit + ? + ? temp ? + + ? external ilimit + ? track enable 300mv 1.2v + ? error amp set r pwrgd 25k 50a 50a 75k 125k track + ? track g m = 8 13a 1.3v v ref 400mv shutdown control 17s delay r pwrgd rising edge in v temp 10mv/c 25c = 250mv shdn 1.22v 100a pwrgd temp i mon = i out 1000 lt3086 3086fa
16 for more information www.linear.com/lt3086 a pplica t ions i n f or m a t ion the lt3086 is a multifunction, low dropout, low noise, linear regulator with shutdown, and adjustable power good. the device supplies 2.1 a with a typical dropout voltage of 330 mv and operates over a wide 1.4 v to 40v input supply range. the operating quiescent current is 1.2ma and drops to less than 1 a in shutdown. the lt3086 regulator optimizes stability and transient response with a minimum low esr 10f ceramic output capacitor. a single resistor sets the output voltage from 0.4 v to 32 v. similarly, a single resis- tor sets the power good threshold. the regulator typically provides 0.1% line regulation and 0.1% load regulation. the lt3086 has convenient programmable diagnostic features. an output current monitor, that is typically 1/1000 of the output current, can set the current limit lower than the typical 2.4 a internal limit. a temperature monitor, that is typically 10 mv/c where 250mv = 25c, can set the thermal limit lower than the typical 165c internal thermal limit. for applications where the voltage error at the load is caused by the resistance in the connections between the lt3086 and the load, programmable cable drop compen- sation cancels the error with a single resistor. multiple lt3086 regulators can be paralleled for higher load cur- rents and heat spreading without the need for external ballast resistors. during load transients where the output overshoots (regulated output voltages of 0.8 v or higher), an internal pull-down current activates pulling about 15 ma from the out pin to ground. the pull- down current is disabled when the output is at or below regulation. the regulator and the output overshoot pull-down turn off when the output voltage is pulled higher than the input by typically 225mv. curves of out over in shutdown threshold appear in the typical performance characteristics section. internal protection circuitry includes reverse-battery pro- tection, reverse - output protection, reverse - current protec - tion, current limit with foldback and thermal shutdown. programming output v oltage the lt3086 has an output voltage range of 0.4 to 32v. the output voltage is programmed with a single resistor, r set , connected from out to the set pin, as shown in figure 1. the set pin has an internal 50 a current source to ground that generates a voltage drop across r set . the device servos the output to maintain the set pin voltage at 0.4 v referenced to ground. calculate the output voltage using the formula in figure 1. curves of set pin reference v oltage and current vs temperature appear in the typical performance characteristics section. 3086 f01 in shdn i mon i lim out set gnd lt3086 v in v imon v out r set r mon v out = i set ? r set + 0.4v i set = 50a r set = v out ? 0.4v 50a output range = 0.4v to 32v figure 1. programming output voltage table 1. output voltage r set values v out (v) r set () v out error for single 1% ideal single 1% dual 1% 1 12k 12.1k 11.8k + 200 0.5% 1.2 16k 16.2k 15.8k + 200 0.8% 1.5 22k 22.1k 21.5k + 511 0.3% 1.8 28k 28k n/a 0% 2 32k 32.4 31.6k + 383 1.0% 2.5 42k 42.2k 41.2k + 825 0.4% 3.3 58k 57.6k 57.6k + 383 C0.6% 5 92k 90.9k 90.9k + 1.1k C1.1% 12 232k 232k n/a 0% table 1 shows the nearest 1% resistor values for some common output voltages, along with the output error caused by not using the ideal resistance value. these errors can be as high as 1% because of the 2% spacing between standard 1% resistors. if tighter output toler- ance is required, consider using more accurate resistors. alternatively, the resistance of r set can be fine-tuned by adding a low value 1% resistor in series, see table 1 dual 1% column. programming power good the adjustable power good threshold is programmed with a single resistor, r pgset , similar to how the output voltage is programmed by r set . similar to the set pin, r pwrgd determines the power good threshold with the lt3086 3086fa
17 for more information www.linear.com/lt3086 a pplica t ions i n f or m a t ion combination of a 0.4 v reference voltage and a precision 50a pull-down current. the power good signal pulls high if the voltage on r pwrgd increases above 0.4 v. built-in hysteresis of typically 0.6% exist for both the 0.4 v volt- age threshold and the 50 a current source. connecting a resistor between the rpwrgd and pwrgd pins can increase the power good hysteresis. see the application circuits for an example. based on the voltage at the load rather than the lt3086s output voltage. in order for the power good threshold to be independent of the cable drop compensations modulation of the lt3086s output voltage as a function of load cur- rent, connect a resistor between cdc and r pwrgd with the same value as r cdc , the resistor between cdc and set. this technique avoids connecting the r pgset resistor to the load voltage through a long trace/wire and eliminates potential stray signal coupling into the r pwrgd pin. see the front page typical application circuit as an example. output voltage noise and transient response the lt3086 regulator provides low output voltage noise over a 10 hz to 100 khz bandwidth while operating at full load. output voltage noise is approximately 65nv/hz over this frequency bandwidth at the unity gain output voltage of 0.4v at 2.1a. to lower output voltage noise for higher output voltages, include a feedforward capacitor, c set , from out to the set pin, as shown in figure 3. a good quality, low leakage capacitor is recommended. this capacitor bypasses the voltage setting resistor, r set , providing a low frequency noise pole. with the use of 10 nf for c set , output voltage noise decreases from 280v rms to 40v rms at 2.1 a when the output voltage is set to 5v. 3086 f03 in shdn i mon i lim out set gnd lt3086 v in v imon v out c out r set r mon c set figure 2. programming power good figure 3. feedforward capacitor for improved transient response the pwrgd pin is the power good open-collector logic output. an internal delay of typically 17s exists only for the rising edge ( when the regulator output voltage rises above the power good threshold) to reject noise or chatter during startup. if the power good function is not needed, leave the r pwrgd and pwrgd pins floating. the power good threshold is typically programmed to 85% to 95% of the regulated output voltage. due to variations in regulator parameters and resistor variations, it is not practi - cal to set the power good threshold greater than 95% of the output voltage. account for load transients where the output voltage droops momentarily before recovering. if increasing output capacitance to reduce output voltage undershoot or if setting the power good threshold lower is not possible, a capacitor, c pgset , from r pwrgd to ground can filter and delay the output signal. this allows for a configurable deglitching period before the power good threshold trips. for example, consider an application with a nominal 1 v output using 10f of output capacitance and the power good threshold set for 90% of v out( nominal) . a 1.5 a output load current step momentarily undershoots v out below the 90% threshold for more than 4s , thus triggering the pwrgd pin to pull low. using a c pgset of greater than 270pf deglitches the power good comparator and prevents the pwrgd pin from pulling low for undershoot events less than 4 s in duration. for applications using cable drop compensation and re - quiring a power good signal, calculate the value of r pgset 3086 f02 in shdn i mon i lim out set gnd lt3086 v in v imon v out v logic or v out r set r mon pwrgd r pwrgd v pwrgd r pgset c pgset (optional) r pgd r pgset = x ? v out(nominal) ? 0.4v 50a where 85% x 95% typically higher values of output voltage noise are often measured if care is not exercised with regard to circuit layout and testing. crosstalk from nearby active signal traces may induce unwanted noise onto the lt3086s output. power supply ripple rejection must also be considered. the lt3086 regulator does not have unlimited power supply rejection and will pass a small portion of the input noise to the output. using a feedforward capacitor, c set , has the added benefit of improving transient response for output voltages greater than 0.4 v. with no feedforward capacitor, the settling time lt3086 3086fa
18 for more information www.linear.com/lt3086 figure 4. transient response vs feedforward capacitor time (s) 0 output voltage deviation (mv) load current (a) 50 ?100 ?200 0 ?250 2 ?50 ?150 3 1 0 50 3086 f04 80 10 60 70 40 20 30 v in = 5.5v v out = 5v c out = 10f c set = 0 c set = 10nf c set = 1nf c set = 100pf ?i l = 210ma to 2.1a and output voltage transients increase as the output voltage is set above 0.4 v. see figure 4 and transient response curves in the typical performance characteristics section. a pplica t ions i n f or m a t ion figure 5. output current monitor and external current limit 3086 f05 in shdn i mon /i lim out set gnd lt3086 v in to adc v imon v out r set r mon i mon = i out 1000 v imon = i mon ? r mon i limit = 1000 ? 0.8v r mon rent limit, typically 2.4 a, is always active and limits output current even if the i lim pin is grounded. in addition, inter- nal current limit foldback overrides external current limit if the v in C v out differential voltage becomes excessive. note that the output current monitor represents not just the load current, but the current into the output capacitor as well. during startup and large load transients, the output current monitor indicates the current required to charge the output capacitor in addition to the load current. to prevent external current limit from engaging prematurely, set the external current limit above the maximum load current to allow the output capacitor to recover without being current limited. for external current limits set for less than 1 a, connect a series 1 k-10nf rc network from i lim to ground to ensure current limit loop stability. adding an rc network from i lim to ground also delays the current monitor signal, allowing output currents higher than the external current limit for a limited duration. this is useful for applications with large output capacitance that would otherwise trigger external current limit during startup and large load transients, slowing output voltage recovery. to guarantee external current limit stability, ensure that the rc network from i lim to gnd has a capacitor value equal to or greater than 10nf and the resistor value is between t c C0.6 and 1k. c is the capacitor value in units of farads. lt c does not recommend an rc network other than the 1k-10nf combination if using the cable drop compensation and paralleling functions. to configure the output current monitor and external cur - rent limit correctly, decide on the necessary current limit and full-scale monitor output voltage. voltage is limited to 0.8v if i mon is tied to i lim . external current limit is typically set 10% to 20% above maximum load current to allow for start-up time is affected by the use of a c set feedforward capacitor. start-up time is directly proportional to the size of the feedforward capacitor and output voltage. settling time to 1% is approximately: t settle = 4.2 t v out t c set 50a see the start-up time vs c set curve in the typical perfor- mance characteristics section. if the lt3086 is configured for cable drop compensation, lt c does not recommend using a feedforward capacitor because c set filters the cdc correction signal and transient response to load current changes degrades. output current monitor and external current limit current out of the i mon pin is typically equal to 1/1000 of the regulators output current. the output current monitor maintains accuracy across the full input voltage range, even during dropout. a resistor, r mon , placed from i mon to ground, sets the voltage scale factor for use with analog-to-digital converters, as shown in figure 5. for example, with 442 for r mon , v imon is set for 0.663v when i out = 1.5a. external current limit activates if the voltage on the i lim pin exceeds the typical 0.8 v threshold. tying the i mon and i lim pins together allows the user to program a desired current limit based on the output current. an internal cur- lt3086 3086fa
19 for more information www.linear.com/lt3086 figure 7. equivalent circuits of i mon and i lim figure 8. kelvin sense connection figure 9. cable drop compensation in i mon i lim 300mv i out /1000 600mv 67k i mon not tied to i lim lt3086 r mon 120k 3086 f07 in i mon i lim 480mv i out /1000 i mon tied to i lim lt3086 r mon 43k a pplica t ions i n f or m a t ion large transient events and i lim threshold variations. for example, if the maximum load current is 1.5 a and both i mon and i lim pins are tied together, an r mon scaling resistor of 442 yields an external current limit of 1.8a. if higher output current monitor voltages are needed, the dfn package offers the ability to separate the i mon and i lim pins with a resistor, as shown in figure 6. to prevent saturation in the i mon output device, choose r mon so that v imon is at least 0.6v less than v in . if external current is not needed, ground the i lim pin. output current monitor accuracy for very low output cur- rents is limited by the offset in the current monitor amplifier and parasitic current paths. the equivalent circuit of the parasitic current paths are shown in figure 7. with zero output load current, the current into r mon is typically 11a when the i mon and i lim pins are tied together. as a result, load currents between 0 ma and 11 ma typically cannot be measured. see current monitor offset curves in the typical performance characteristics section. load regulation and cable drop compensation output load regulation for the lt3086 is typically 0.1%. optimal regulation is obtained when the r set feedback resistor is connected to the out pin of the regulator. in high current applications, small voltage drops appear due to the resistances of pcb traces or wires between the regulator and the load. these drops may be eliminated by connecting r set directly to the output at the load as shown in figure 8. note that the voltage drop across r out and r rtn add to the dropout voltage of the regulator. the voltage drop across r gnd should also be minimized to reduce output voltage error due to ground pin current. see gnd pin current curves in the typical performance characteristics section. the lt3086 has cable drop compensation ( cdc) func - tionality that allows delivery of well regulated voltage to remote loads using only two wires of known fixed resistance. compensation is user programmed by con - necting a resistor, r cdc , between the set and cdc pins, as shown in figure 9. at zero load current, the cdc pin typically regulates to the same voltage as the set pin. the voltage decreases at a rate equal to 1/3 of the change in i mon voltage. for example, if v imon increases from 0 to 0.6v , v cdc decreases 3086 f09 in shdn i mon i lim out set gnd lt3086 v in c load (optional) r set r cdc r mon cdc c out r line2 r line1 l line1 r esr (optional) l line2 load r cdc = r mon ? r set 3000 ? r wire r wire = r line1 + r line2 3086 f08 in shdn i mon i lim out set gnd lt3086 v in r mon r gnd r rtn r out r set load figure 6. separate i mon and i lim (dfn package only) 3086 f06 in shdn i mon i lim out set gnd lt3086 v in v imon to adc v out r set r lim r opt (dfn package only) r mon = r lim + r opt i limit = 1000 ? 0.8v r lim lt3086 3086fa
20 for more information www.linear.com/lt3086 figure 10. transient response with cable drop compensation 0 80 160 560 640 720 800 240 320 400 480 time (s) output voltage (v) load current (a) 3086 f10 5.8 5.6 5.2 4.8 4.4 2 5.4 5.0 4.6 4.2 1 0 v in = 6v r mon = 357 r wire = 0.24 r cdc = 46.4k r set = 92k c out = 10f c load = 0 v out with cdc v load without cdc v load with cdc ?i load = 0.5a to 1.5a a pplica t ions i n f or m a t ion by 0.2 v. as a result, the current that flows through r cdc is proportional to load current which increases the voltage across r set , effectively increasing output voltage. r cdc is selected using the following equation so that the voltage at the out pin increases to cancel the voltage drop in the cables connected to the load. r cdc = r mon ? r set 3000 ? r wire where r wire is the total resistance of the supply and return cabling connecting the lt3086 to the load. figure 10 shows the transient response with cable drop compensation. with compensation, the output voltage at the load remains nearly constant. note that the transient voltage droop in output voltage is about the same as the voltage droop with no compensation, but with the output voltage returning to the correct compensated voltage. in shdn i mon i lim out set gnd lt3086 master v out v in v track = v ilim(master) r set r mon 3086 f011 in shdn i mon i lim out set track gnd lt3086 slave(s) r mon figure 11. master/slave(s) configuration for paralleling there are limits to the amount of voltage drop that can be compensated using cable drop compensation. using cable drop compensation subjects load regulation to the variability of the current monitor voltage output and the cabling resistance. lt c recommends limiting cable drop compensation to 20% of v out for applications needing good regulation. the limiting factor is variations in wire temperature as copper wire resistance changes about 19% for a 50 c temperature change. if output regulation requirements are loose ( e.g., when using a secondary regulator), cable drop compensation of up to 50% may be used. noise from the current monitor output affects noise seen at the output. filtering the current monitor output with an rc network from i lim to ground is effective at reducing this noise source, especially at light loads. consult the output current monitor and external current limit section for more information paralleling multiple regulators the lt3086 has been specifically designed to make paral - leling multiple r egulators together easy. paralleling enables applications to increase total output current and to spread heat dissipated by the regulator over a wider area on the pcb. the parallel scheme is based on a master/slave principle, where one lt 3086 is designated as master, and the other regulators act as slaves with active sharing of total load current, as shown in figure 11. the slaves internal current tracking amplifier compares the current monitor output from the master with the current monitor output seen at the slaves i lim pin, and servos the slaves output current to match the masters. if long cables are used, an additional supply bypass capacitor, c load , should be added directly to the load to handle large load transient conditions. c out must still directly connect to the out pin to ensure stable operation of the lt3086, minimizing output capacitor esr and esl. long cables have inductance where a resonance forms between the wire inductance, l wire and c load . damping is accomplished by adding series resistance, r esr , to c load . the value of r esr is approximately: r esr = 2 ? l wire c load lt3086 3086fa
21 for more information www.linear.com/lt3086 a pplica t ions i n f or m a t ion the master lt3086 is connected exactly the same as a single regulator where its output current monitor voltage seen at its i lim pin is used as the common current tracking signal. the slave devices connect this signal to their track pins to make their output current equal to the masters. the track pin has an internal pull-up current that is typically 15a at 0.75v. when the track pin is unused, the pin is pulled up and clamped at 1.25 v, disabling the current tracking amplifier. when the track pin is con - nected to the master current tracking signal, the track pin voltage is pulled below the 1.2 v threshold, enabling the current tracking amplifier and disabling the slaves 50 a reference current, i set . disabling the reference current ensures that the master is the only device controlling the output voltage. set the maximum master current tracking signal to less than 0.8 v to prevent external current limit from triggering prematurely. to prevent the slave current tracking amplifier from ever being disabled, the slave track pin must be tied to the master i lim pin. the master i lim pin has an internal 1 v clamp that is below the slave 1.2v current tracking amplifier enable threshold. when multiple slaves are used, a smaller master r mon resistor should be used to compensate for the pull-up currents from all the track pins of the slaves. for ex - ample, a master sourcing 2.1 a typically has 0.697 v at its i lim pin with an r mon resistor of 332. referring to the track pin pull-up current curve in the typical perfor- mance characteristics , with 0.697 v on the track pin, each slave typically adds 15 a to the masters 2.1ma i mon output. for an application with 5 slaves connected, decrease r mon s value to: r mon = 0.697v [2.1ma + 5 ? 15a ( ) ] = 325 ? the closest 1% resistor value equals 324. all slave regulators must have their set pins connected to the master set pin. the track amplifier operates by adjusting the slave internal reference voltage slightly as a function of the difference in master and slave current monitor voltages. this has a strong effect on the slave output current, which forces the slave output current to match the master. mismatch between master and slave internal reference voltages and current monitor outputs, offset in the slave track amplifier and track pin pull-up currents all contribute to output current sharing error. in the case of negative offset, a slave runs less current than the master. at very light loads, negative offset enables the slave output overshoot pull-down circuit, forcing the master to supply current to keep the output voltage within regulation. as a result, quiescent current may increase for very light loads in the master/slave configuration. in some applications, multiple regulators may be spaced some distance apart to optimize heat distribution. that makes the use of low resistance traces important to con - nect each regulator to the local ground system and to avoid ground loops created by load currents. ground currents can be as high as 30 ma at 1.5 a and 50 ma at 2.1 a, for each regulator. limiting differential ground pin voltages to less than 10 mv minimizes tracking errors. ground trace resistance between master and slaves should be less than 10mv/30ma = 0.33 at 1.5 a load, and 10mv/50ma = 0.2 for 2.1a load. output capacitance the lt3086 regulator is stable with a wide range of output capacitors. the esr of the output capacitor affects stabil - ity, most notably with small capacitors. use a minimum output capacitor of 10 f with an esr of 0.1 or less to prevent oscillations. the output load transient response is a function of output capacitance. larger values of output capacitance decrease the peak deviations and provide im - proved transient response for larger load current changes. for applications with large load current transients, a low esr ceramic capacitor in parallel with a bulk tantalum capacitor often provides an optimally damped response. for example, a 47 f tantalum capacitor with esr = 0.1 in parallel with the 10 f ceramic capacitor with esr < 0.01 reduces output deviation by about 2:1 for large transient loads and increases loop phase margin. give extra consideration to the use of ceramic capacitors. manufacturers make ceramic capacitors with a variety of dielectrics, each with different behavior across tempera- ture and applied voltage. the most common dielectrics are specified with eia temperature characteristic codes of z5u, y5v, x5r and x7r. the z5u and y5v dielectrics lt3086 3086fa
22 for more information www.linear.com/lt3086 dc bias voltage (v) change in value (%) 3086 f12 20 0 ?20 ?40 ?60 ?80 ?100 0 4 8 10 2 6 12 14 x5r y5v 16 both capacitors are 16v, 1210 case size, 10f temperature (c) ?50 40 20 0 ?20 ?40 ?60 ?80 ?100 25 75 3086 f13 ?25 0 50 100 125 y5v change in value (%) x5r both capacitors are 16v, 1210 case size, 10f figure 12. ceramic capacitor dc bias characteristics figure 13. ceramic capacitor temperature characteristics a pplica t ions i n f or m a t ion provide high c-v products in a small package at low cost, but exhibit strong voltage and temperature coefficients, as shown in figures 12 and 13. when used with a 5 v regulator, a 16v 10 f y5v capacitor can exhibit an effective value as low as 1 f to 2 f for the dc bias voltage applied, and over the operating temperature range. the x5r and x7r dielectrics yield much more stable characteristics and are more suitable for use as the output capacitor. the x7r type works over a wider temperature range and has better temperature stability, while the x5r is less expensive and is available in higher values. care still must be exercised when using x5r and x7r capacitors; the x5r and x7r codes only specify operating temperature range and maximum capacitance change over temperature. capacitance changes due to dc bias is less with x5r and x7r capacitors, but can still be significant enough to drop capacitor values below appropriate levels. capacitor dc bias characteristics tend to improve as component case size increases, but expected capacitance at operating voltage should be verified . v oltage and temperature coefficients are not the only sources of problems. some ceramic capacitors have a piezoelectric response. a piezoelectric device generates voltage across its terminals due to mechanical stress, similar to the way a piezoelectric accelerometer or mi - crophone works. for a ceramic capacitor, the stress is induced by vibrations in the system or thermal transients. the resulting voltages produced can cause appreciable amounts of noise. input capacitance low esr ceramic input bypass capacitors are acceptable for applications with short input and ground leads. however, applications connecting a power supply to the lt3086 using long wires are prone to voltage spikes, reliability concerns and application-specific board oscillations. the input wire inductance found in many battery-powered applications, combined with the low esr ceramic capacitor , forms a high-q lc resonant tank circuit. in some instances this resonant frequency beats against the output current dependent ldo bandwidth and interferes with proper operation. simple circuit modifications are then required. this behavior is not indicative of lt3086 instability, but is a common application issue. the self-inductance, or isolated inductance, of a wire is directly proportional to its length. wire diameter is not a major factor on its self-inductance. for example , the self- inductance of a 2- awg isolated wire (diameter = 0.26 ") is about half the self-inductance of a 30- awg wire ( diameter = 0.01 "). one foot of 30- awg wire has approximately 465nh of self-inductance. tw o methods can reduce wire self-inductance. one method divides the current flowing towards the lt3086 between two parallel conductors. in this case, the farther apart the wires are from each other, the more the self-inductance is reduced; up to a 50% reduction when placed a few inches apart. splitting the wires connects two equal inductors in parallel, but placing them in close proximity creates mutual inductance add - ing to the self-inductance. the second and most effective way to reduce overall inductance is to place both forward lt3086 3086fa
23 for more information www.linear.com/lt3086 a pplica t ions i n f or m a t ion and return current conductors ( the input and gnd wires) in very close proximity. tw o 30- awg wires separated by only 0.02 ", used as forward- and return-current conduc - tors, reduce the overall self-inductance to approximately one-fifth that of a single isolated wire. if a battery, mounted in close proximity, powers the lt3086 , a 10 f input capacitor suffices for stability. however, if a distant supply powers the lt3086, use a larger value input capacitor. use a rough guideline of 1f ( in addition to the 10f minimum) per 8 inches of wire length. the minimum input capacitance needed to stabilize the application also varies with power supply output impedance variations. placing additional capacitance on the lt3086 s output also helps. however, this requires an order of magnitude more capacitance in comparison with additional lt3086 input bypassing. series resistance between the supply and the lt3086 input also helps stabilize the application; as little as 0.1 to 0.5 suffices. this impedance dampens the lc tank circuit at the expense of dropout voltage. a bet - ter alternative is to add additional input capacitance with higher esr at the input, such as tantalum or electrolytic capacitors, or by adding resistance in series with a low esr ceramic capacitor. overload recovery like many ic power regulators, the lt3086 has safe operating area protection. the safe operating area protec - tion decreases current limit as input-to-output voltage increases, and keeps the power transistor inside a safe operating region for all values of input-to-output voltage. the lt3086 provides some output current at all values of input- to-output voltage up to the specified 45 v operational maximum. current limit foldback overrides external current limit ( if used) if v in C v out voltage differential becomes excessive. when power is first applied, the input voltage rises and the output follows the input; allowing the regulator to start-up into very heavy loads. during start-up, as the input voltage is rising, the input-to-output voltage differential is small, allowing the regulator to supply large output currents. with a high input voltage, a problem can occur wherein the removal of an output short will not allow the output to recover. other regulators, such as the lt1083/lt1084/ lt1085 family and lt1764 a also exhibit this phenomenon, so it is not unique to the lt3086. the problem occurs with a heavy output load when the input voltage is high and the output voltage is low. common situations are immediately after the removal of a short-circuit or if the shutdown pin is pulled high after the input voltage is already turned on. the load line intersects the output current curve at two points creating two stable output operating points for the regulator. with this double intersection, the input power supply needs to be cycled down to zero and brought up again for the output to recover. thermal considerations the power handling capability of the lt3086 is limited by the maximum rated junction temperature of 125 c. three components comprise the power dissipated by the device: 1. output current multiplied by the input/output voltage differential: i out ? (v in ? v out ), 2. gnd pin current multiplied by the input voltage: i gnd ? v in , and 3. current monitor current multiplied by the input/current monitor voltage differential: i mon ? (v in ? v imon ) gnd pin current is determined using the gnd pin current curves in the typical performance characteristics section. power dissipation equals the sum of the three components listed above. the lt3086 regulators have internal thermal limiting that protects the device during overload conditions. for continuous normal conditions, the maximum junction temperature of 125 c must not be exceeded. carefully consider all sources of thermal resistance from junction- to- ambient including other heat sources mounted in proximity to the lt3086. the underside of the lt3086 dfn and tssop packages have exposed metal (10.5mm 2 ) from the lead to the die attachment. these packages allow heat to directly transfer from the die junction to the printed circuit board metal. the dual-in-line pin arrangement allows metal to extend lt3086 3086fa
24 for more information www.linear.com/lt3086 a pplica t ions i n f or m a t ion beyond the ends of the package on the topside ( component side) of a pcb. connect this metal to gnd on the pcb. the multiple in and out pins of the lt3086 also assist in spreading heat to the pcb. for surface mount devices, heat sinking is accomplished by using the heat spreading capabilities of the pc board and its copper traces. copper board stiffeners and plated through-holes also can spread the heat generated by power devices. tables 2 and 3 list thermal resistance for several topside copper areas on a fixed board size. all measurements were taken in still air on a 4- layer fr-4 board with 1 oz solid internal planes and 2 oz top/bottom external trace planes with a total board thickness of 1.6 mm. the four layers were electrically isolated with no thermal vias present. achieving low thermal resistance necessitates attention to detail and careful pcb layout. for more information on thermal resistance and high thermal conductivity test boards, refer to jedec standard jesd51, notably jesd51 - 12 and jesd51-7. the use of thermal vias, increased copper weight, and air flow, will improve the resultant thermal resistance. table 2. measured thermal resistance for dhd and fe package copper area board area (mm 2 ) thermal resistance (junction-to-ambient) topside* (mm 2 ) backside (mm 2 ) 2500 2500 2500 25c/w 1000 2500 2500 26c/w 225 2500 2500 28c/w 100 2500 2500 33c/w *device is mounted on topside table 3. measured thermal resistance for r package copper area board area (mm 2 ) thermal resistance (junction-to-ambient) topside* (mm 2 ) backside (mm 2 ) 2500 2500 2500 15c/w 1000 2500 2500 16c/w 225 2500 2500 19c/w *device is mounted on topside measured thermal resistance for t7 package thermal resistance (junction-to-case) = 3c/w. the lt3086 has the ability to check thermal performance by observing the output current and temperature monitor pins. the effects of heat sinking, the enclosure, and any air movement can be instantly analyzed without special instrumentation. calculating junction temperature example: given an output voltage of 5 v, an input voltage range of 6v 5%, a maximum output current range of 1a with 698 for r mon , and a maximum ambient temperature of 75 c, what will the maximum junction temperature be? the power dissipated by the device equals: i out(max) ? (v in(max) ? v out ) + i gnd ? v in(max) + i mon(max) ? (v in(max) ? v imon(max) ) where, i out(max) = 1a v in(max) = 6.3v i gnd at (i out = 1a, v in = 6.3v) = 11ma v imon at (i out = 1a, r mon = 698) = 0.698v so: p = 1a ? (6.3v ? 5v) + 11ma ? 6.3v + 1ma ? (6.3v ? 0.698v) = 1.38w using a dfn package, the thermal resistance will be in the range of 25 c/w to 33 c/w depending on the topside cop- per area. so the junction temperature rise above ambient approximately equals: 1.38 w ? 30c/w = 41.4c the maximum junction temperature equals the maximum ambient temperature plus the maximum junction tempera - ture rise above ambient or: t jmax = 75c + 41.4c = 116.4c protection features the lt3086 regulator incorporates several protection features that make it ideal for use in battery-powered circuits. in addition to the normal protection features lt3086 3086fa
25 for more information www.linear.com/lt3086 figure 16. out over in shutdown threshold figure 14. reverse-output current figure 15. output overshoot pull-down current a pplica t ions i n f or m a t ion associated with monolithic regulators, such as current limiting and thermal limiting, the devices also protect against reverse-input voltages, reverse-output voltages, and reverse-output-to-input voltages. current limit protection and thermal overload protection protect the device against current overload conditions at the output of the device. the typical thermal shutdown temperature is 165 c and incorporates about 7 c of hys - teresis. for normal operation, do not exceed the maximum rated junction temperature of 125c. the lt3086 in pin withstands reverse voltages of 45v . the device limits current flow to less than 2ma ( typically less than 1 a) and no negative voltage appears at out. the device protects both itself and the load against batteries that are plugged in backwards. the lt3086 incurs no damage if its output is pulled be - low ground . if the input is left open-circuit or grounded, the output can be pulled below ground by 36 v. no cur- rent flows through the pass transistor from the output. however, current flows in ( but is limited by) the feedback resistors r set , that sets the output voltage, and r rpwrgd , that sets the power good threshold. current flows from the internal clamps in the set and r pwrgd pins to the external circuitry pulling out below ground. if the input is powered by a voltage source, the device protects itself by turning off the power device when the internal clamps activate. if schottky diodes are used to prevent the set and r pwrgd pins from activating their internal clamps, the output sources current equal to its current limit capability and the lt3086 protects itself by thermal limiting. in this case, grounding the shdn pin turns off the device and stops the output from sourcing current. reverse current flow follows the curve shown in figure 14. the lt3086 incurs no damage if the set and r pwrgd pins are pulled above ground up to 36 v. if the input is left open-circuit or grounded, the set pin performs like a large resistor (typically 80k) in series with a diode. in circuits where a secondary supply raises the output voltage above the regulated voltage set by r set , the output overshoot circuitry pulls current from the output pin to ground as long as the output voltage is below the input voltage. output overshoot current follows the curve shown output voltage (v) 3086 f14 0 20 32 4 24 28 16 8 12 reverse output current (ma) 0.6 0.5 0.3 0.1 0.4 0.2 0 t j = 25c v in = 0v v out = v set = v rpwrgd current flows through pins to ground out, r pwrgd set output voltage (v) 3086 f15 0 20 36 32 4 24 28 168 12 output overshoot pull-down (ma) 30 25 15 5 20 10 0 t j = 25c v in = 0v v out = v set = v rpwrgd current flows through out pin to gnd temperature (c) ?75 out over in shutdown threshold (mv) 300 275 225 175 150 100 50 250 200 125 75 25 0 100 ?25 3086 f16 175 0?50 125 150 7525 50 on to off off to on in figure 15. when the output voltage is pulled above the input by typically 225 mv, the lt3086 shuts down as shown in figure 16 and the 15 ma overshoot pull-down current source turns off. lt3086 3086fa
26 for more information www.linear.com/lt3086 typical a pplica t ions 2.5v low noise regulator with power good 1.2v, 1.5a low noise regulator with 1.8a external current limit 5 white led driver with pwm dimming and led open detection 10f in temp i lim gnd out lt3086 r set 42.2k 1% set v in 3.1v to 13v v out 2.5v at 2.1a 10f shdn c set 10nf i mon v temp 10mv/c 25c = 250mv pwrgd v pwrgd high when v out > 90% of 2.5v r pwrgd r pgd 100k r pgset 37.4k 1% 3086 ta09 10f in temp i lim shdn gnd out lt3086 r set 15.8k 1% set v in 1.65v to 16v v out 1.2v at 1.5a 10f c set 10nf i mon v temp 10mv/c 25c = 250mv 200 1% r mon 442 1% v mon 0.8v at 1.8a full-scale 3086 ta10 3086 ta11 10f in i mon i lim shdn gnd out lt3086 r mon 800 r set ** 1% set v in * v out r1 1k c1 10nf 10f note: adjust r mon to set maximum led current (set to 800 for 1a) drive pwm low to turn off led string (pulse to dim) *input voltage required is dependent on the led string voltage **choose r set and r pgset based on led string pwrgd r pwrgd r pgd 100k 1% r pgset ** 1% v pwrgd high for open led condition pwm lt1004-1.2 r2 3.32k 1% r3 9.09k 1% r4 100k 1% lt3086 3086fa
27 for more information www.linear.com/lt3086 typical a pplica t ions ensuring external current limit stability for i lim 1a increasing current monitor output voltage increasing power good hysteresis (ex: 2%) in shdn i mon v imon 800mv at 250ma additional r-c network i lim out set gnd lt3086 v in 12.5v to 40v v out 12v at 200ma 10f 10f r set 232k 1% r lim 3.24k 1% r1 1k 3086 ta04 c set 10nf c1 10nf in shdn i mon v imon = 1v/a i limit = 1.5a i lim out set gnd lt3086 (dhd only) v in 3v to 19v v out 2.5v at 1.2a 10f 10f r set 41.2k 1% r lim 536 1% r1 464 1% 3086 ta05 c set 10nf r lim = 0.8v i limit ? ? ? ? ? ? ? 1000 3086 ta06 in shdn i mon i lim out set gnd lt3086 v out 3.3v at 1.5a r set 57.6k 1% r pgset 51.1k 1% r mon 442 1% v in 3.85v to 18v 10f 10f pwrgd r pwrgd v pwrgd r hys 3.65m 1% r pgd 100k r hys = v x ? 100 p ? v out ? 0.4v ( ) v out h ?h int ( ) 50a ( ) where, v x = r pgd termination voltage = v out p = power good trip threshold (% of v out ) h = desired percentage hysteresis h int = 0.6 (internal percentage hysteresis) adjustable voltage controlled current source 3086 ta12 10f in set i lim shdn gnd out lt3086 track v in * 10f i mon v track adjust from 0v to 750mv for 0a to 2.1a constant current *restrict input voltage range to limit power dissipation and prevent foldback current limit from interfering with proper operation r mon 357 1% r1 1k c1 10nf 400mv in gnd out lt6650 fb 1f 1f load lt3086 3086fa
28 for more information www.linear.com/lt3086 typical a pplica t ions load current monitoring using power good in shdn i mon i lim out set pwrgd r pwrgd gnd lt3086 v in 3.85v to 18v v out 3.3v at 1.5a 10f 10f c1 (optional, for powergood flag delay) r set 57.6k 1% r1 169 1% r2 324 1% r pgd 100k 3086 ta03 v pwrgd high when i load > 1.25a i limit = 1.6a r1 = 0.8v i limit ? ? ? ? ? ? ? 1000 ?r2 r2 = 0.4v i load ? ? ? ? ? ? ? 1000 input undervoltage detector using power good programming thermal limit temperature 3086 ta07 in shdn i mon i lim out set gnd lt3086 v out 3.3v at 1.5a r set 57.6k 1% r pgset 71.5k 1% r mon 442 1% v in 4v to 18v 10f 10f pwrgd r pwrgd v pwrgd high when v in > 4v r pgd 100k in shdn i mon temp v temp 10mv/c 25c = 250mv 124c thermal limit i lim out set gnd lt3086 v in 2.4v to 12v v out 1.8v at 2.1a 10f 10f r set 28k 1% r mon 332 1% r temp 12.4k 1% 3086 ta08 c set 10nf r temp = v temp 100a paralleling tw o regulators for 5v, 4.2a v in 5.7v to 15v 10f 10f 10f 10f c set 10nf in shdn i mon i lim out set gnd lt3086 master v out 5v at 4.2a v out v ilim(master) 0.7v at 4.2a r set 90.9k 1% v temp(slave) 10mv/c 25c = 250mv v temp(master) 10mv/c 25c = 250mv 1.1k 1% r mon 332 1% 3086 ta02 in shdn i mon i lim out set track gnd lt3086 slave r mon 332 1% temp temp r pwrgd r pgset 82.5k 1% r pgd 100k v pwrgd pwrgd lt3086 3086fa
29 for more information www.linear.com/lt3086 p ackage descrip t ion please refer to http://www .linear.com/designtools/packaging/ for the most recent package drawings. 4.00 0.10 (2 sides) 5.00 0.10 (2 sides) note: 1. drawing proposed to be made variation of version (wjgd-2) in jedec package outline mo-229 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package 0.40 0.10 bottom view?exposed pad 2.44 0.10 (2 sides) 0.75 0.05 r = 0.115 typ 4.34 0.10 (2 sides) 1 8 16 9 pin 1 top mark (see note 6) 0.200 ref 0.00 ? 0.05 (dhd16) dfn rev a 1113 0.25 0.05 pin 1 notch 0.50 bsc 4.34 0.05 (2 sides) recommended solder pad pitch and dimensions 2.44 0.05 (2 sides) 3.10 0.05 0.50 bsc 0.70 0.05 4.50 0.05 package outline 0.25 0.05 dhd package 16-lead plastic dfn (5mm 4mm) (reference ltc dwg # 05-08-1707 rev a) lt3086 3086fa
30 for more information www.linear.com/lt3086 p ackage descrip t ion fe16 (bb) tssop rev j 1012 0.09 ? 0.20 (.0035 ? .0079) 0 ? 8 0.25 ref 0.50 ? 0.75 (.020 ? .030) 4.30 ? 4.50* (.169 ? .177) 1 3 4 5 6 7 8 10 9 4.90 ? 5.10* (.193 ? .201) 16 1514 13 12 11 1.10 (.0433) max 0.05 ? 0.15 (.002 ? .006) 0.65 (.0256) bsc 2.94 (.116) 0.195 ? 0.30 (.0077 ? .0118) typ 2 recommended solder pad layout 0.45 0.05 0.65 bsc 4.50 0.10 6.60 0.10 1.05 0.10 2.94 (.116) 3.05 (.120) 3.58 (.141) 3.58 (.141) 4.70 (.185) millimeters (inches) note: 1. controlling dimension: millimeters 2. dimensions are in 3. drawing not to scale 4. recommended minimum pcb metal size for exposed pad attachment see note 4 note 5 note 5 6.40 (.252) bsc fe package 16-lead plastic tssop (4.4mm) (reference ltc dwg # 05-08-1663 rev j) exposed pad variation bb 5. bottom exposed paddle may have metal protrusion in this area. this region must be free of any exposed traces or vias on pbc layout *dimensions do not include mold flash. mold flash shall not exceed 0.150mm (.006") per side detail a detail a is the part of the lead frame feature for reference only no measurement purpose 0.56 (.022) ref 0.53 (.021) ref detail a please refer to http://www .linear.com/designtools/packaging/ for the most recent package drawings. lt3086 3086fa
31 for more information www.linear.com/lt3086 p ackage descrip t ion r (dd7) 0212 rev f .026 ? .035 (0.660 ? 0.889) typ .143 +.012 ?.020 ( ) 3.632 +0.305 ?0.508 .050 (1.27) bsc .013 ? .023 (0.330 ? 0.584) .095 ? .115 (2.413 ? 2.921) .004 +.008 ?.004 ( ) 0.102 +0.203 ?0.102 .050 .012 (1.270 0.305) .059 (1.499) typ .045 ? .055 (1.143 ? 1.397) .165 ? .180 (4.191 ? 4.572) .330 ? .370 (8.382 ? 9.398) .060 (1.524) typ .390 ? .415 (9.906 ? 10.541) 15 typ .420 .350 .585 .090 .035 .050 .325 .205 .080 .585 recommended solder pad layout for thicker solder paste applications recommended solder pad layout .090 .035 .050 .420 .276 .320 note: 1. dimensions in inch/(millimeter) 2. drawing not to scale .300 (7.620) .075 (1.905) .183 (4.648) .060 (1.524) .060 (1.524) .256 (6.502) bottom view of dd pak hatched area is solder plated copper heat sink r package 7-lead plastic dd pak (reference ltc dwg # 05-08-1462 rev f) detail a detail a 0 ? 7 typ 0 ? 7 typ please refer to http://www .linear.com/designtools/packaging/ for the most recent package drawings. lt3086 3086fa
32 for more information www.linear.com/lt3086 p ackage descrip t ion .050 (1.27) .026 ? .036 (0.660 ? 0.914) t7 (to-220) 0801 .135 ? .165 (3.429 ? 4.191) .700 ? .728 (17.780 ? 18.491) .045 ? .055 (1.143 ? 1.397) .165 ? .180 (4.191 ? 4.572) .095 ? .115 (2.413 ? 2.921) .013 ? .023 (0.330 ? 0.584) .620 (15.75) typ .155 ? .195* (3.937 ? 4.953) .152 ? .202 (3.860 ? 5.130) .260 ? .320 (6.604 ? 8.128) .147 ? .155 (3.734 ? 3.937) dia .390 ? .415 (9.906 ? 10.541) .330 ? .370 (8.382 ? 9.398) .460 ? .500 (11.684 ? 12.700) .570 ? .620 (14.478 ? 15.748) .230 ? .270 (5.842 ? 6.858) bsc seating plane *measured at the seating plane t7 package 7-lead plastic to-220 (standard) (reference ltc dwg # 05-08-1422) please refer to http://www .linear.com/designtools/packaging/ for the most recent package drawings. lt3086 3086fa
33 for more information www.linear.com/lt3086 information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. r evision h is t ory rev date description page number a 6/14 added mp-grade for tssop, dd-pak, and to-220 packages 2 to 4 added ec table line item for minimum load current and note 16 3, 5 added and modified two gnd pin current curves, two psrr at 1a curves, two line regulation curves and modified v out noise curve 7 to 12 updated thermal resistance for dhd, fe and r packages 2, 24 updated dhd package description 29 lt3086 3086fa
34 for more information www.linear.com/lt3086 ? linear technology corporation 2013 lt 0614 rev a ? printed in usa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com/lt3086 r ela t e d p ar t s typical a pplica t ion part number description comments lt1764/ lt1764a 3a, fast transient response, low noise ldo 340mv dropout voltage, low noise: 40v rms , v in : 2.7v to 20v, to-220 and dd packages, -a version stable also with ceramic capacitors lt1963/ lt1963a 1.5a, low noise, fast transient response ldo 340mv dropout voltage, low noise: 40v rms , v in : 2.5v to 20v, -a version stable with ceramic capacitors, to-220, dd-pak, sot-223 and so-8 packages lt1965 1.1a, low noise, low dropout linear regulator 310mv dropout voltage, low noise: 40v rms , v in : 1.8v to 20v, v out : 1.2v to 19.5v, stable with ceramic capacitors, to-220, dd-pak, msop and 3mm 3mm dfn packages lt3022 1a, low voltage vldo linear regulator 145mv dropout voltage, v in : 0.9v to 10v, v out : 0.2v to 9.5v, stable with low esr, ceramic output capacitors, 16-pin dfn (5mm 3mm) and 16-lead msop packages lt3070 5a, low noise, programmable v out , 85mv dropout linear regulator with digital margining 85mv dropout voltage, digitally programmable v out : 0.8v to 1.8v, digital output margining: 1%, 3% or 5%, low output noise: 25v rms ; directly parallelable, stable with low esr ceramic output capacitors (15f minimum), 28-lead 4mm 5mm qfn package lt3071 5a, low noise, programmable v out , 85mv dropout linear regulator with analog margining 85mv dropout v oltage, digitally programmable v out : 0.8v to 1.8v, analog margining: 10%, low output noise: 25v rms ; directly parallelable, i mon output current monitor, stable with low esr ceramic output capacitors (15f minimum), 28-lead 4mm 5mm qfn package lt3080/ lt3080-1 1.1a, parallelable, low noise, low dropout linear regulator 300mv dropout voltage (2-supply operation), low noise: 40v rms , v in : 1.2v to 36v, v out : 0v to 35.7v, current-based reference with 1-resistor v out set; directly parallelable (no op amp required), stable with ceramic capacitors; to-220, dd-pak, sot-223, msop and 3mm 3mm dfn-8 packages; -1 version has integrated internal ballast resistor lt3081 1.5a, single resistor rugged linear regulator with monitors extended safe operating area, v in : 1.2v to 36v, v out : 0v to 34.5v, current-based reference, programmable current limit, output current and temperature monitors lt3083 3a, parallelable, low noise, low dropout linear regulator 310mv dropout voltage (2-supply operation), low noise: 40v rms , v in : 1.2v to 23v, v out : 0v to 22.6v, current-based reference with 1-resistor v out set, directly parallelable (no op amp required), stable with ceramic capacitors; to-220, dd-pak, tssop, 4mm 4mm dfn-12 packages lt3085 500ma, parallelable, low noise, low dropout linear regulator 275mv dropout (2-supply operation), low noise: 40v rms , v in : 1.2v to 36v, v out : 0v to 35.7v, current-based reference with 1-resistor v out set, directly parallelable (no op amp required), stable with ceramic capacitors; ms8e and 2mm 3mm dfn-6 packages paralleling tw o regulators for 5v, 4.2a with cable drop compensation (cdc) v in 6.4v to 15v for r wire = 0.2 10f 10f r line1 cable 10f 10f in shdn i mon i lim out set gnd lt3086 master v out v ilim(master) 0.7v at 4.2a r set 90.9k + 1.1k 1% v temp(slave) 10mv/c 25c = 250mv v load 5v at 4.2a v temp(master) 10mv/c 25c = 250mv r cdc 1% r mon 332 1% 3086 ta13 in shdn i mon i lim out set track gnd lt3086 slave r mon 332 1% r line2 temp temp cdc load r cdc = r mon ? r set x + 1 ( ) ? 3000 ? r wire r wire = r line1 + r line2 where x = number of slaves lt3086 3086fa

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